Physical Design Engineer

Physical Design Engineer

Join a pioneering startup as they build the compute platform for AGI! This innovative company creates vertically integrated solutions from silicon to systems, tailored for massive ML workloads. They seek silicon physical design engineers to develop high-performance, sustainable GenAI silicon.

Successful candidates will deliver performant, functionally accurate silicon for compute, memory management, high-speed connectivity, and other critical technologies in advanced process nodes. Be part of this groundbreaking team shaping the future of AI hardware engineering!

Job Description: Physical Design Engineer

Responsibilities:

• Contribute scalable solutions to silicon and physical design methodology across blocks, subsystems, and full-chip designs.
• Lead chip-level physical design tasks including floor-planning, placement, routing, optimizations, timing closure, and verification.
• Drive reviews and progress reporting based on key PPA metrics.
• Collaborate closely with design, DFT, and other stakeholders.
• Coordinate with design services partners and third-party vendors on block-level and chip-level closure.

Requirements:

• Extensive RTL-to-silicon experience in driving physical design for subsystems and/or top-level functions within ASICs and SOCs, spanning from early RTL design and netlist to production silicon.
• Proven track record in floor planning, place and route, clock tree insertion and analysis, timing analysis, physical verification, electrical sign-off, and related areas to generate tapeout ready GDS for large physical blocks and/or top-level designs.
• Project experience collaborating with design, verification, and DFT teams to optimize design partitioning for PPA and sign-off.
• Experience working with third-party design services partners, preferably involved in taking subsystems and/or top-level designs from initial floor plan to sign-off and tapeout.