Engineer: FPGA Design - II
Engineer: FPGA Design - II
Infobahn Softworld Inc
San Jose, CA
See who Infobahn Softworld Inc has hired for this role
Title: FPGA/ RTL Design Engineer
Location: San Jose, California
Duration: 8 Months - GC/USC
Onsite
Minimum Educational Requirement: Bachelors, masters preferred- Computer Engineering, Electrical Engineering, Electronics Engineering.
Location: San Jose, California
Duration: 8 Months - GC/USC
Onsite
- Digital logic design experience in Verilog/SystemVerilog
- Experience in developing unit level testbenches with Verilog/SystemVerilog
- Experience with simulation tools like VCS and Modelsim
- Knowledge of industry standard Memory Mapped and Streaming protocols including AMBA AXI protocols.
- Familiarity with network-on-chip (NoC) topologies and design methodology.
- Experience in FPGA design and familiarity with FPGA design tools - Intel FPGA Quartus, Xilinx Vivado, Vitis etc.
- Experience in timing closure for high speed FPGA designs
- Knowledge of scripting in tcl, perl or python.
Minimum Educational Requirement: Bachelors, masters preferred- Computer Engineering, Electrical Engineering, Electronics Engineering.
-
Seniority level
Mid-Senior level -
Employment type
Full-time -
Job function
Other -
Industries
IT Services and IT Consulting
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