Design Verification Engineers

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Type of Hire: W2 Fulltime permanent 

Role –Design Verification Engineer :10 Positions (SoC-5, PCIe-5)

Location: Bay Area, CA/Austin TX

Free health insurance

PTOs: 10 Business days (Including sick leaves)                                                     

Job Title

Design Verification Engineers :10 Positions (SoC-5, PCIe-5)

Architect block and full-chip verification environments using HVLs and constrained random

techniques for SOCs with embedded CPUs and mixed signal interfaces. Requires UVM, System Verilog, SVA 

○ Develop test plans and coverage metrics from specifications and write block and chip-level

tests in C,SV,UVM

○ Debug RTL and Gate simulations and work with design engineers to verify fixes.

○ Replicate silicon bugs in simulation environments and validate fixes or SW workarounds.

○ Convert verification tests to test patterns and assist Test Engineers on ATE vector bringup.

○ Evaluate latest verification methodologies and develop scripts etc. to automate verification

flows.

Skills