Design Verification Engineer

We are seeking a highly skilled Verification Engineer with a minimum of 5 years of experience in the verification domain. The ideal candidate must have hands-on experience with System Verilog and UVM, and a solid understanding of the complete verification life cycle. The role requires expertise in SOC Integration and SOC verification, along with protocol experience in HBI, HBM, UCIe, PCIe, Ethernet, LPDDR5, and DFT.

Key Responsibilities:

Develop and execute verification plans, test benches, and test cases to ensure high-quality deliverables.

Implement and utilize System Verilog and UVM for verification processes.

Conduct thorough verification throughout the verification life cycle, from test plan creation to coverage closure.

Perform SOC Integration and SOC verification, ensuring seamless protocol implementation and validation.

Collaborate with design and development teams to identify and resolve verification issues.

Analyze and debug test failures, identifying root causes and implementing corrective actions.

Utilize protocol experience in HBI, HBM, UCIe, PCIe, Ethernet, LPDDR5, and DFT to ensure robust verification coverage.

Maintain detailed documentation of verification processes, methodologies, and results.