Design Verification Engineer

As an Architect for block and full-chip verification environments, you would be responsible for designing and implementing verification strategies using advanced verification techniques. This role focuses on System-on-Chips (SOCs) that incorporate embedded CPUs and mixed signal interfaces.

Key Responsibilities:

1. Architecture Design: You will architect block and full-chip verification environments using Hardware Verification Languages (HVLs) and constrained random techniques. This involves utilizing industry-standard methodologies like Universal Verification Methodology (UVM), System Verilog, and assertion-based verification (SVA).
2. Test Development: Develop comprehensive test plans and coverage metrics based on design specifications. Write block-level and chip-level tests using a combination of C, System Verilog (SV), and UVM.
3. Simulation and Debugging: Debug RTL (Register Transfer Level) and Gate-level simulations to identify and resolve issues. Collaborate closely with design engineers to verify and validate fixes in the design.
4. Bug Replication and Validation: Replicate silicon bugs in simulation environments and validate fixes or software workarounds. This involves a deep understanding of the design and its intended functionality.
5. ATE Vector Bringup Support: Convert verification tests into test patterns suitable for Automatic Test Equipment (ATE). Assist Test Engineers in the setup and validation of ATE vectors.
6. Methodology Evaluation and Automation: Stay updated with the latest verification methodologies and tools. Develop scripts and automation flows to streamline verification processes and improve efficiency.

Required Skills:

• Proficiency in HVLs such as System Verilog and methodologies like UVM.
• Experience with constrained random verification techniques.
• Strong understanding of SOC architectures, embedded CPUs, and mixed signal interfaces.
• Ability to develop test plans, coverage metrics, and verification tests.
• Expertise in debugging RTL and Gate-level simulations.
• Familiarity with ATE vector bringup and test pattern conversion.
• Scripting skills for automation (e.g., Python, Perl) are desirable.

Preferred Qualifications:

• Prior experience in verifying complex SOC designs.
• Knowledge of industry-standard tools and methodologies for verification.
• Strong analytical and problem-solving skills.
• Ability to work effectively in a collaborative team environment.

This role requires a deep technical understanding of verification methodologies and the ability to apply them to complex SOC designs. You will play a critical role in ensuring the functional correctness and quality of the SOC products through rigorous verification processes.